The present invention relates to a semiconductor device and, more particularly, to improvements in variations in characteristics and characteristic deterioration in a ferroelectric memory device.
As conventional semiconductor devices, there have been developed various circuits from relatively small-sized integrated circuits mounting, for example, an amplifier circuit, an oscillating circuit, a power supply circuit and the like, to relatively large-sized integrated circuits, such as a microprocessor and a memory device. Especially in recent years, as a kind of non-volatile memory device, a ferroelectric memory device with ferroelectric capacitors as capacitors constituting memory cells has been contrived.
The ferroelectric capacitor consists of a pair of electrodes opposite to each other, and a dielectric layer comprising a ferroelectric material and sandwiched between both electrodes, and has the hysteresis characteristic as a relationship between a voltage applied between the both electrodes and polarizability of the ferroelectric material. That is, the ferroelectric capacitor has a construction in which even when the electric field (applied voltage) is zero, a remaining polarization of a polarity in accordance with the hysteresis of voltage application remains in the ferroelectric layer, and in the ferroelectric memory device non-volatility of the storage data is realized by representing storage data by the remaining polarization of the ferroelectric capacitor.
In a non-volatile memory device using such ferroelectric capacitors, it is an important objective to reduce variations in the hysteresis characteristics of the ferroelectric capacitors and reduce changes in the hysteresis characteristic accompanying the use.
More specifically, FIGS. 14 to 16 are diagrams for explaining a conventional ferroelectric memory device, FIG. 14 is a plan view illustrating a memory cell array in the ferroelectric memory device, FIG. 15 is a cross-sectional view along a line XVxe2x80x94XV portion in FIG. 14, and FIG. 16 is a plan view illustrating a position relation between upper electrodes and a lower electrode of ferroelectric capacitors.
In the figures, reference numeral 200 designates a memory cell array constituting a ferroelectric memory device, a plurality of transistor regions 220a are arranged on a silicon substrate 201 in a first direction D1, and an insulating film 202 for element isolation is formed on a portion of the silicon substrate 201, except the transistor regions 220a. 
On both sides of the transistor regions 220a in a line along the first direction D1, lower electrodes (first electrodes) 211 are formed as cell plate electrodes on the insulating film 202 for element isolation via first interlayer insulating films 203. The lower electrode 211 comprises a metallic material, such as titanium and platinum, and has a stripe-shaped plan configuration extending along the first direction D1. On surfaces of the lower electrodes 211, ferroelectric layers 213 are formed.
On the ferroelectric layers 213 on the surfaces of the lower electrodes 211, upper electrodes (second electrodes) 212 comprising a metallic material, such as titanium and platinum, are formed corresponding to the respective transistor regions 220a. That is, on the ferroelectric layers 213, the plurality of upper electrodes 212 are arranged along the first direction D1. A plan shape of each upper electrode 212 is a rectangular shape having the first direction D1 as its longitudinal direction, and as is known from FIG. 14, the area of each upper electrode 212 is smaller than that of the lower electrode 211. Here, ferroelectric capacitors 210 are constituted by the lower electrode 211, the upper electrodes 212, and the ferroelectric layer 213 located between these electrodes, and the surfaces of the ferroelectric layers 213 and the surfaces of the upper electrodes 211 are covered with second interlayer insulating films 204.
In this case, the upper electrode 212 is disposed in a center portion of the lower electrode 211, and the distance O11 (hereinafter referred to as non-overlap width) between a side 211a1 of the lower electrode 211 and a side 211a1 of the upper electrode 211 opposite thereto is made equal to the distance O12 (hereinafter referred to as non-overlap width) between the other side 211a2 of the lower electrode 211 and a side 211a2 of the upper electrode 211 opposite thereto.
Between the pair of lower electrodes 211 that sandwich the transistor regions 220a opposing to each other, a pair of word lines (second wirings) 223a and 223b comprising polysilicon are disposed so as to straddle over the plurality of transistor regions 220a arranged in a line. A source diffusion region 222 and drain diffusion regions 221 of a memory transistor 220 constituting a memory cell are formed on both sides of the word lines 223a and 223b in each transistor region 220a. Portions of the word lines 223a and 223b located above each transistor region 220a constitute gate electrodes of the memory transistor 220, and are located on the substrate surface via gate insulating films 202a. The surfaces of the diffusion regions 221 and 222 and the word lines 223a and 223b are covered with the first and second interlayer insulating films 203 and 204. In FIG. 14, these interlayer insulating films are not shown.
The source diffusion region 222 located between the pair of word lines 223a and 223b in each transistor region 220a is connected to a bit line 233b extending along a second direction D2 perpendicular to the first direction D1, through a contact hole 205b formed in the first and second interlayer insulating films 203 and 204. The drain diffusion regions 221 located outside the opposite word lines 223a and 223b in each transistor region 220a are electrically connected to the upper electrodes 212 by connecting wirings 233a. That is, one end of the connecting wiring 233a is connected to the upper electrode 212 through a contact hole 204a formed in the second interlayer insulating film 204, and the other end of the connecting wiring 233a is connected to the drain diffusion region 221 through a contact hole 205a formed in the first and second interlayer insulating films 203 and 204.
The lower electrodes 211 and the ferroelectric layers 213 are formed by successively forming films of a metallic material, such as titanium and platinum, and a ferroelectric material on the interlayer insulating film 203 and patterning these films, and the upper electrodes 212 are formed by forming a film of a metallic material, such as titanium and platinum, on the ferroelectric layer 213 and patterning the film. The bit lines 233b and the connecting wirings 233a are formed by patterning a metallic film, such as aluminum, formed on the interlayer insulating film 204. The word lines 223a and 223b are formed by patterning a polysilicon film that is formed on the gate insulating films 202a and the insulating film 202 for element isolation.
The first interlayer insulating film 203 comprises an insulating material, such as NSG (oxide silicon based) and BPSG (boron, phosphine doped oxide silicon), and the second interlayer insulating film 204 comprises, for example, PSG (phosphine doped oxide silicon).
As the ferroelectric material composing the ferroelectric layer 213 of the ferroelectric capacitors, KNO3, PbLa2O3-ZrO2-TiO2, PbTiO3-PbZrO3 or the like has been known. In addition, PCT International Publication WO 93/12542 discloses a ferroelectric material that has extremely low fatigueness as compared with PbTiO3-PbZrO3, being suitable for a ferroelectric memory device.
The operation will be described briefly.
In the ferroelectric memory device with the construction as described above, when, for example, the word line 223a is selected and subsequently, one of the lower electrodes 211 (for example, the uppermost lower electrode shown in FIG. 14) is driven, thereby making the voltage level thereof the level corresponding to the logical voltage xe2x80x9cHxe2x80x9d, storage data of the ferroelectric capacitors 210 formed on this lower electrode are read out onto the respective bit lines 233b through the connecting wirings 233a and the transistors 220.
A brief description is given of the principle of this reading out operation. FIG. 17 is a graph showing the hysteresis characteristic of the ferroelectric capacitor, in which the ordinate represents the polarization charge amount P of the ferroelectric capacitor and the abscissa represents the electric field E applied to the ferroelectric capacitor. P1 and P2 show the polarization charge amounts that are generated when the electric fields E1 and E2 (=xe2x88x92E1) are applied to the ferroelectric capacitor, respectively, Pr1 shows the residual charge amount against the applied voltage E1, Pr2 shows the residual charge amount against the applied voltage E2 (=xe2x88x92E1), Ec1 shows the counter electric field against the residual charge amount Pr2, and Ec2 shows the counter electric field against the residual charge amount Pr1. In this ferroelectric memory device, the reading out voltage that is applied to the ferroelectric capacitor at reading out of data (that is, the voltage applied to the lower electrode) is set to a voltage that makes the electric field applied to the ferroelectric capacitor, E2.
In the ferroelectric memory device, predetermined storage data are written into the respective memory cells, and the residual charge amount of the ferroelectric capacitor constituting the memory cell corresponds to the residual charge amount Pr1 or Pr2 corresponding to the storage data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, respectively. In this state, when a predetermined word line is driven and the reading out voltage is applied to a predetermined lower electrode of ferroelectric capacitors, the electric charge corresponding to the residual charge amount Pr1 or Pr2 is read out from each ferroelectric capacitor that is positioned on the predetermined lower electrode onto the bit line.
For example, the difference xcex94P2 (=Pr2xe2x88x92P2) between the polarization charge amount P2 corresponding to the applied voltage E2 and the residual charge amount Pr2 is read out from the ferroelectric capacitor having the residual charge amount Pr2 as signal charges corresponding to the storage data onto the bit line 233b. Further, the difference xcex94P1 (=Pr1xe2x88x92P2 ) between the polarization charge amount P2 corresponding to the applied voltage E2 and the residual charge amount Pr1 is read out from the ferroelectric capacitor having the residual charge amount Pr1 as signal charges corresponding to the storage data onto the bit line. In this case, since the charge amount (Pr1xe2x88x92P2 ) and the charge amount (Pr2xe2x88x92P2 ) that are read out onto the bit lines are different from each other, it is possible to discriminate the data that are stored in the memory cells due to the difference in the charge amount. In addition, in the construction in which the data are read out from the ferroelectric capacitors as described above, as for the memory cell in which the residual charge amount of the ferroelectric capacitor is the residual charge amount Pr1, data destruction occurs by the reading out operation. For this reason, the ferroelectric memory device has a circuit construction in which after reading out of data, the storage data before reading out is written into each ferroelectric capacitor to modify the data of the memory cell.
Then, the signal charges corresponding to the storage data that are read out onto the respective bit lines 233b are amplified by sense amplifiers (not shown) to be output to the outside of the ferroelectric memory device. Thereafter, the voltage level of the lower electrode 211 is made a level corresponding to the logical voltage xe2x80x9cLxe2x80x9d to make the word line 223a the unselected state, thereby completing the reading out.
In the conventional ferroelectric capacitors 210, however, variations in the characteristics, i.e., variations in polarizability of the ferroelectric layers, are large, and changes in the characteristic, i.e., changes in polarizability with passage of time are likely to occur.
More specifically, the initial values of the polarization charge amounts P1 and P2, the counter electric fields Ec1 and Ec2, or the residual charge amounts Pr1 and Pr2 against the applied fields E1 and E2 in the hysteresis characteristic curves of the ferroelectric capacitor shown in FIG. 17 widely vary between the memory cells in one device (ferroelectric memory device) or between the devices, and changes in the hysteresis characteristic with passage of time (change from normal characteristic shown by curves La to deteriorated characteristic shown by curves Lb) are likely to occur in a short time.
The present invention is directed to solving the above-described problems, and has an object to provide a semiconductor device with large longevity and a good fabrication yield, in which variations in characteristics of ferroelectric capacitors can be suppressed and characteristic changes with passage of time can be reduced.
A semiconductor device according to the present invention includes a first electrode extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; second electrodes disposed opposite to the first electrode and having a plan configuration of the size in the first direction and the size in the second direction being equal to each other, or a plan configuration of the size in the first direction being shorter than the size in the second direction; and a ferroelectric layer disposed between the first electrode and the second electrodes; the first and second electrodes and the ferroelectric layer between the both electrodes constituting ferroelectric capacitors. in preferably the second electrodes are formed by patterning a predetermined conductive material layer, the plurality of second electrodes are arranged along the first direction, and the arrangement intervals between the adjacent second electrodes are set to be the minimum size of an opening pattern that can be formed on the conductive material layer. in more preferably a plan configuration of the second electrode is a polygonal configuration, and all the sizes of respective angles in the plan configuration of the second electrode are larger than 90xc2x0.
In another embodiment, the device includes first electrodes extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; a plurality of second electrodes positioned opposite to the first electrodes and arranged in the form of a matrix along the first direction and the second direction; and ferroelectric layers disposed between the first electrodes and the second electrodes; the first electrodes, the ferroelectric layers, and the plurality of second electrodes constituting a plurality of ferroelectric capacitors.
Preferably, the second electrodes have a plan configuration of the size in the first direction and the size in the second direction being equal to each other, or a plan configuration of the size in the first direction being shorter than the size in the second direction.
In another embodiment, the device includes a first electrode extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; second electrodes disposed opposite to the first electrode and having a plan configuration having a direction between the first direction and the second direction as its longitudinal direction; and a ferroelectric layer disposed between the first electrode and the second electrodes; the first and second electrodes and the ferroelectric layer between the both electrodes constituting ferroelectric capacitors.
Preferably a plan configuration of the second electrode is a polygonal configuration, and all the sizes of respective interior angles in the plan configuration of the second electrode are larger than 90xc2x0.
In another embodiment, the device includes a first electrode extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; second electrodes disposed opposite to the first electrode and having a first side that is closest and opposite to a first side of the first electrode parallel to the first direction, and a second side that is closest and opposite to a second side of the first electrode parallel to the first direction; and a ferroelectric layer disposed between the first electrode and the second electrodes; the first and second electrodes and, the ferroelectric layer between the both electrodes constituting ferroelectric capacitors; and the length of the first side of the second electrode being larger than the length of the second side thereof, and the distance between the first side of the second electrode and the first side of the first electrode being longer than the distance between the second side of the second electrode and the second side of the first electrode.
Preferably a plan configuration of the second electrode is a polygonal configuration, and all the sizes of respective interior angles in the plan configuration of the second electrode are larger than 90xc2x0.
In another embodiment, the device constitutes a ferroelectric memory device with a plurality of memory cells respectively comprising ferroelectric capacitors and memory transistors and arranged in the form of a matrix, cell plate lines for driving the ferroelectric capacitors, a plurality of bit lines corresponding to respective memory cell columns, a plurality of word lines corresponding to respective memory cell rows, for selecting the memory transistors, and sense amplifiers connected to the respective bit lines and amplifying data signals on the predetermined bit lines. This ferroelectric memory device includes first electrodes extending along a first direction, having a plan configuration having a second direction perpendicular to the first direction as its width direction, and connected to the cell plate lines; second electrodes disposed opposite to the first electrodes and having a plan configuration of the size in the first direction and the size in the second direction being equal to each other, or a plan configuration of the size in the first direction being shorter than the size in the second direction; and ferroelectric layers disposed between the first electrodes and the second electrodes; the first and second electrodes and the ferroelectric layers constituting the ferroelectric capacitors.
Preferably, the device includes a first electrode constituting the ferroelectric capacitors extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; second electrodes constituting the ferroelectric capacitors disposed opposite to the first electrode; a ferroelectric layer constituting the ferroelectric capacitors disposed between the first electrode and the second electrodes; an insulating film formed to cover the surfaces of the second electrodes and having contact holes formed on positions of the surfaces of the second electrodes that are shifted from the center positions to one side of the first electrode along the first direction; and wirings formed on the insulating film and connected to the second electrodes through the contact holes.
Alternatively, the device includes a first electrode constituting the ferroelectric capacitors extending along a first direction and having a plan configuration having a second direction perpendicular to the first direction as its width direction; second electrodes constituting the ferroelectric capacitors disposed opposite to the first electrode; a ferroelectric layer constituting the ferroelectric capacitors disposed between the first electrode and the second electrodes; an insulating film formed to cover the surfaces of the second electrodes and having contact holes formed on predetermined positions of the surfaces of the second electrodes; and wirings formed on the insulating film and electrically connected to the second electrodes; the second electrodes having a structure in which the whole is divided into plural electrode portions by forming notches at predetermined sides; and the wirings being connected to parts of the plural electrode portions constituting the second electrodes through the contact holes.